Technical Field
The present disclosure generally relates to the identification of slave devices on a local communications network. More particularly, but not exclusively, the present disclosure relates to dynamically defining addresses of slave devices coupled to the local communications network.
Description of the Related Art
In many electronic systems, it is desirable to control peripheral devices using data passed across a local communications network. One such network includes a multi-conductor bus that follows an INTER-INTEGRATED CIRCUIT (I2C) protocol. The I2C protocol created by PHILIPS SEMICONDUCTOR governs data communications between compatible I2C devices over two wires. Devices that conform to the I2C protocol send information serially over a pair of electrical conductors wherein one conductor is used to pass data (SDA) and one conductor is used to pass a clock (SCL) signal.
FIG. 1 is a schematic diagram of a system 1 coupling five conventional devices 2, 4, 6, 8, 10 in accordance with an I2C protocol. In the system 1, a conventional master device 2 is communicatively coupled to a first conventional slave device 4, a second conventional slave device 6, a third conventional slave device 8, and a fourth conventional slave device 10. The five conventional devices are commonly coupled together with a serial clock line (SCL) 12 and a serial data line (SDA) 14. Collectively, the SCL 12 line and the SDA 14 line may be referred to as a “bus.”
The I2C protocol provides for conventional master devices and conventional slave devices. A conventional master device 2 directs operations on the bus at a present time. That is, the conventional master device 2 controls the clock SCL 12 and generates START and STOP signals. Conventional slave devices 4, 6, 8, 10 monitor activity on the bus and act on control commands and data passed on the bus by the conventional master device 2. Correspondingly, when conventional slave devices 4, 6, 8, 10 are driving the bus to communicate data, the conventional master device 2 will monitor bus activity. Monitoring by the conventional devices typically includes sampling by Schmitt Trigger inputs, but other monitoring circuitry is also considered.
The conventional master device 2 can send data to any of the conventional slave devices 4, 6, 8, 10, and the conventional master device 2 can receive data from any of the conventional slave devices 4, 6, 8, 10. The conventional slave devices 4, 6, 8, 10 cannot directly transfer data between themselves. Instead, one conventional slave device must first pass the data to the conventional master device 2, and the conventional master device 2 must re-communicate the data to the other conventional slave device. In addition, since the I2C protocol makes no provisions for direct slave-to-slave communications, in order to carry out such data transfer, the conventional devices of system 1 must be particularly arranged for such operations.
In the system 1 of FIG. 1, a single conventional master device 2 is illustrated. The I2C protocol provides for multiple conventional master devices in a single system, but this is not shown in FIG. 1. Multi-master operations are more complex and include particular arbitration of the bus and particular clock synchronization, but such operations are not necessary to the understanding of the present disclosure.
According to the I2C protocol, the SCL 12 and SDA 14 lines operate bi-directionally. Thus, any of the conventional devices on the bus are permitted to drive either line. Both lines of the I2C bus will idle in a logic “high” state (i.e., HIGH or HI), and to this end, both the SCL 12 and SDA 14 lines are arranged as open-collector/open-drain outputs. Each line is pulled to its logic HIGH state using, for example, a resistor that electrically couples the subject line to a source voltage. Typically, resistance values range from about 1 kΩ to 10 kΩ, but other resistances are also considered. In this case, pullup currents are typically 1 mA or less.
This I2C physical architecture implements a wired logical “AND” function such that any conventional device on the bus that forces (e.g., pulls) voltage down causes all of the other conventional devices on the bus to detect logic “low” data bit value (i.e., LOW or LO). Conversely, to communicate a logic HIGH data bit value on one of the bus lines, all devices stop driving that particular bus line, and the line is pulled HIGH. Typically, supply voltages for an I2C bus range from 1.2V to 5.5V, but other voltages are also used in some implementations.
In the system of FIG. 1, information is communicated across the bus serially. That is, data bits are communicated during a timed assertion and release of the SCL 12 line by one device on the bus such that clock pulses are detected by all of the conventional devices on the bus. Concurrently, to pass either logic HIGH data bit values or logic LOW data bit values, the one conventional device controlling the bus also coordinates timed assertion and release of the SDA 14 line with the clock pulses of the SCL 12 line. The other non-driving (e.g., “listening”) conventional devices on the bus use the detected clock pulses to direct a sampling operation on the SCL 12 and SDA 14 lines and thereby capture the serially communicated bits of data.
In a conventional I2C data transfer operation, the bus (i.e., SCL 12 and SDA 14) is operated to indicate a START condition, which includes raising both the clock line SCL 12 and the data line SDA 14 HIGH, and, while the SCL 12 line is HIGH, driving the SDA 14 line LOW.
Subsequently, after the START condition is asserted, the SCL 12 line is controllably asserted and released to generate a clock pulse pattern on the SCL 12 line.
Conventional clock speeds on an I2C bus may range from zero to 100 kHz and other, faster clock speeds (e.g., up to 400 kHz, up to 3.4M Hz, and faster) are also contemplated.
Concurrent to the clock pulses formed with the SCL 12 line, a first byte of data is serially communicated on the bus, bit-by-bit, by conventional master device 2. The first byte contains a conventional slave device address and a direction that data will flow. In an exemplary case, the address is 7 bits long, followed by a data direction bit. The address is transferred with the most significant bit first, and the data direction bit will indicate whether one or more subsequent bytes will be provided by the conventional master device 2 (i.e., the data direction bit indicates a “write” operation) or whether one or more subsequent bytes will be provided by the addressed conventional slave device (i.e., the data direction bit indicates a “read” operation).
In a system 1 that includes a local I2C communication network, conventional slave devices are identified by different addresses, each of which is unique across the network. With respect to FIG. 1, each conventional slave is assigned a 7-bit address, but addresses having different lengths (e.g., 10 bits) are also contemplated. In some cases, all of the bits of a conventional slave device address are internally and unchangeably fixed. In some cases, some bits of the conventional slave device address are internally defined while other bits of the slave address are externally configured at the time of system manufacture. In still other cases, such as in FIG. 1, all of the bits of a conventional slave device address are defined at the time of system manufacture.
The assignment of an address to each conventional slave device, as illustrated in the system 1 of FIG. 1, is carried out by wiring defined address pins of the conventional slave devices 4, 6, 8, 10, to either HIGH or LOW voltage potentials. In this way, “generic” conventional slave devices may be provided by manufacturers, and systems integrators may hard-wire each conventional device with a desired unique address.
With respect to the conventional slave devices of FIG. 1, the first conventional slave device 4 is wired with an address “3” (i.e., 000 0011B), the second conventional slave device 6 is wired with an address “7” (i.e., 000 0111B), the third conventional slave device 8 is wired with an address “11” (i.e., 000 1011B), and the fourth conventional slave device 10 is wired with an address “15” (i.e., 000 1111B).
After the first byte of data is transferred by the conventional master device 2, which includes the conventional slave device address, the addressed conventional slave device will acknowledge its recognition of the first byte by passing an acknowledgement bit (ACK). Once the acknowledgement bit is passed, data will be transferred across the bus. The direction that data will be transferred is determined by the data direction bit that was passed as part of the first data byte communicated by the conventional master device 2.
In cases where the data direction bit indicated a write operation, the conventional master device 2 will maintain control of the SCL 12 line, and the conventional master device 2 will communicate one or more subsequent data bytes to the addressed conventional slave. In cases where the data direction bit indicated a read operation, the addressed conventional slave device will control the SCL 12 line, and the conventional slave device will communicate one or more data bytes to the conventional master device 2. The conventional device (i.e., the conventional master 2 or the addressed conventional slave device) that receives the subsequent data will assert an ACK bit on the bus after the data is successfully received.
After passing one or more bytes of data over the communication bus, communications will end when a STOP condition is asserted on the communication bus. In a conventional I2C data transfer operation, asserting the STOP condition includes raising the clock SCL 12 line HIGH, releasing the SDA 14 line so that it falls LOW, and raising the SDA 14 line HIGH while the SCL 12 line remains HIGH.
Communications between the conventional master device 2 and one or more conventional slave devices 4, 6, 8, 10 may be ongoing according to the operations of the conventional master and slave devices. In some cases, for example, the data passed by the conventional master device 2 to a particular conventional slave device is a command, which is acted on by the particular conventional slave device. Communications may operate according to a particular protocol. One such conventional protocol is defined in an I2C-BUS SPECIFICATION AND USER MANUAL, UM10204, Rev. 6-4 April 2014, which is provided by NXP and included herein by reference.
All of the subject matter discussed in the Background section is not necessarily prior art and should not be assumed to be prior art merely as a result of its discussion in the Background section. Along these lines, any recognition of problems in the prior art discussed in the Background section or associated with such subject matter should not be treated as prior art unless expressly stated to be prior art. Instead, the discussion of any subject matter in the Background section should be treated as part of the inventor's approach to the particular problem, which in and of itself may also be inventive.